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CNF-MIM: The Future of Ultra-Thin Capacitors
By creating an array of vertical and free-standing carbon nanofibers (CNF) and using them as a scaffold for metal-insulator-metal (MIM) layers, Smoltek Semi creates CNF-MIM capacitors that can be placed directly under processors while taking up minimal space. These CNF-MIM capacitors deliver more energy storage capacity closer to where it’s needed most, while requiring fewer manufacturing steps than competing technologies. The result is a capacitor that not only performs better but also costs less to produce – addressing both the technical and economic challenges of powering tomorrow’s electronics.
A Clear Technology Roadmap
| Parameter | Gen-One (2025) | Gen-Two (2026) | Gen-Three (2027) |
| Capacitance density | 745 nF/mm² | 1,704 nF/mm² | 3,097 nF/mm² |
| Equivalent Series Resistance (ESR) | 50 mΩ | 20 mΩ | 10 mΩ |
| Die Thickness (before casing) | 100 µm | 80 µm | 60 µm |
Our development follows a structured generational pathway, with each milestone bringing significant performance improvements:
- Gen-Zero (Completed 2024): Our initial proof-of-concept, executed in collaboration with Yageo Group, has successfully demonstrated functional capacitors with proper coating of high-aspect-ratio carbon nanofibers without creating short circuits or leakage paths.
- Gen-One (Underway 2025): Initial technology validation shows promising results with longer carbon nanofibers maintaining the same device footprint. We’re targeting nearly tripled volumetric capacitance density while reducing ESR by a factor of 30. Test units will be available for customer evaluation during Q4 2025, providing crucial real-world performance data.
- Gen-Two (Target 2026): Moving toward volume production, we’ll maintain the same device area while making capacitors 20% thinner. The 1,704 nF/mm² capacitance density will enable applications in advanced mobile processors where space constraints are critical, while the 20 mΩ ESR meets requirements for higher-frequency filtering in modern computing architectures.
Gen-Three (Target 2027): Our most advanced target aims to be 40% thinner than Generation Zero while delivering over 12 times more capacitance. The projected 10 mΩ ESR will enable direct chip integration for AI accelerators and high-performance computing, where ultra-low power delivery impedance is essential for stable operation under variable workloads.