CNF-MIM: The Future of Ultra-Thin Capacitors

By cre­at­ing an array of ver­ti­cal and free-stand­ing car­bon nanofibers (CNF) and using them as a scaf­fold for met­al-insu­la­tor-met­al (MIM) lay­ers, Smoltek Semi cre­ates CNF-MIM capac­i­tors that can be placed direct­ly under proces­sors while tak­ing up min­i­mal space. These CNF-MIM capac­i­tors deliv­er more ener­gy stor­age capac­i­ty clos­er to where it’s need­ed most, while requir­ing few­er man­u­fac­tur­ing steps than com­pet­ing tech­nolo­gies. The result is a capac­i­tor that not only per­forms bet­ter but also costs less to pro­duce – address­ing both the tech­ni­cal and eco­nom­ic chal­lenges of pow­er­ing tomorrow’s electronics.

A Clear Technology Roadmap

Para­me­ter	Gen-One (2025)	Gen-Two (2026)	Gen-Three (2027)
Capac­i­tance density	745 nF/​mm²	1,704 nF/​mm²	3,097 nF/​mm²
Equiv­a­lent Series Resis­tance (ESR)	50 mΩ	20 mΩ	10 mΩ
Die Thick­ness (before casing)	100 µm	80 µm	60 µm

Our devel­op­ment fol­lows a struc­tured gen­er­a­tional path­way, with each mile­stone bring­ing sig­nif­i­cant per­for­mance improvements:

• Gen-Zero (Com­plet­ed 2024): Our ini­tial proof-of-con­cept, exe­cut­ed in col­lab­o­ra­tion with Yageo Group, has suc­cess­ful­ly demon­strat­ed func­tion­al capac­i­tors with prop­er coat­ing of high-aspect-ratio car­bon nanofibers with­out cre­at­ing short cir­cuits or leak­age paths.
• Gen-One (Under­way 2025): Ini­tial tech­nol­o­gy val­i­da­tion shows promis­ing results with longer car­bon nanofibers main­tain­ing the same device foot­print. We’re tar­get­ing near­ly tripled vol­u­met­ric capac­i­tance den­si­ty while reduc­ing ESR by a fac­tor of 30. Test units will be avail­able for cus­tomer eval­u­a­tion dur­ing Q4 2025, pro­vid­ing cru­cial real-world per­for­mance data.
• Gen-Two (Tar­get 2026): Mov­ing toward vol­ume pro­duc­tion, we’ll main­tain the same device area while mak­ing capac­i­tors 20% thin­ner. The 1,704 nF/​mm² capac­i­tance den­si­ty will enable appli­ca­tions in advanced mobile proces­sors where space con­straints are crit­i­cal, while the 20 mΩ ESR meets require­ments for high­er-fre­quen­cy fil­ter­ing in mod­ern com­put­ing architectures.

Gen-Three (Tar­get 2027): Our most advanced tar­get aims to be 40% thin­ner than Gen­er­a­tion Zero while deliv­er­ing over 12 times more capac­i­tance. The pro­ject­ed 10 mΩ ESR will enable direct chip inte­gra­tion for AI accel­er­a­tors and high-per­for­mance com­put­ing, where ultra-low pow­er deliv­ery imped­ance is essen­tial for sta­ble oper­a­tion under vari­able workloads.