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Compatibility Assessment of CVD growth of Carbon nanofibers on bulkCMOS devices
Research paper published in Nano Letters 2008, Volume 8, Issue 8, pp. 2437–2441, July 18, 2008.
We compare the level of deterioration in the basic functionality of individual transistors on ASIC chips fabricated in standard 130 nm bulk CMOS technology when subjected to three disparate CVD techniques with relatively low processing temperature to grow carbon nanostructures. We report that the growth technique with the lowest temperature has the least impact on the transistor behavior.
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