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Research paper published in the proceedings of 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019, pp. 1870-1876.
A M Saleem, R Andersson, M Bylund, C Goemare, G Pacot, S Kabir, V Desmaris • August 26, 2019
ComÂplete on-chip fulÂly solÂid-state 3D inteÂgratÂed capacÂiÂtors using verÂtiÂcalÂly aligned carÂbon nanofibers as elecÂtrodes to proÂvide a large 3D surÂface in a MIM conÂfigÂuÂraÂtion have been manÂuÂfacÂtured and charÂacÂterÂized in terms of capacÂiÂtance per device footÂprint area, equivÂaÂlent series resisÂtance (ESR), breakÂdown voltÂage and leakÂage curÂrent. The entire manÂuÂfacÂturÂing process of the capacÂiÂtors is comÂpleteÂly CMOS comÂpatÂiÂble, which along with the low device proÂfile of about 4 μm makes the devices readÂiÂly availÂable for inteÂgraÂtion on a CMOS-chip, in 3D stackÂing, or redisÂtriÂbÂuÂtion layÂers in a 2.5D interÂposÂer techÂnolÂoÂgy. CapacÂiÂtances of 200 nF/​mm2 , ESR of about 100 mΩ, breakÂdown voltÂages of 25 V and leakÂage curÂrent of the order of 0.004 A/​F have been measured.
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