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Research paper published in the proceedings of 2nd PCNS Passive Components Networking Symposium, Bucharest, Romania, 10–13 September, 2019. Award for outstanding paper.
Complete on-chip fully solid-state 3D integrated capacitors using vertically aligned carbon nanofibers as electrodes to provide a large 3D surface in a MIM configuration have been manufactured and characterized. The capacitance per device footprint area has been studied, as well as its behavior at different temperatures and frequencies. Equivalent series resistance (ESR), breakdown voltage and leakage current have also been measured. The entire manufacturing process of the capacitors is completely CMOS compatible, and in combination with the low device profile of about 4 µm this makes the devices readily available for integration on a CMOS-chip, in 3D stacking, or redistribution layers in a 2.5D interposer technology. Capacitances of ca 350 nF/mm2, ESR of about 100 mΩ, breakdown voltages of up to 25 V and leakage currents in the order of 0.004 nA/nF have been measured.
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Research
October 2, 2021
Research paper published in the proceedings at the 3rd PCNS 7-10th September 2021, Milano, Italy as paper No.5.3. and voted by attendees as: BEST PAPER AWARD.
Research
November 26, 2020
Research paper presented in the proceedings of the 53rd International Symposium on Microelectronics, IMAPS 2020, October 5-8, 2020.
Research
August 5, 2020
Research paper published in the proceedings of 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020, pp. 1614-1619.
Research
October 26, 2019
Research paper published in the proceedings of 2nd PCNS Passive Components Networking Symposium, Bucharest, Romania, 10–13 September, 2019. Award for outstanding paper.