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Research paper published in the proceedings of 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018, pp. 2313-2318.
R Andersson, A M Saleem, V Desmaris • August 9, 2018
ComÂplete on-chip fulÂly solÂid-state 3D inteÂgratÂed capacÂiÂtors using verÂtiÂcalÂly aligned carÂbon nanofibers as elecÂtrodes to proÂvide a large 3D surÂface in a MIM conÂfigÂuÂraÂtion have been manÂuÂfacÂtured and charÂacÂterÂized in terms of capacÂiÂtance per device footÂprint area. The fibers are grown directÂly on the botÂtom elecÂtrode surÂface and then conÂforÂmalÂly coatÂed with a dielecÂtric mateÂrÂiÂal using atomÂic layÂer depoÂsiÂtion. Two difÂferÂent dielecÂtric mateÂriÂals, Al2O3 and HfO2 , of difÂferÂent thickÂnessÂes have been invesÂtiÂgatÂed, and difÂferÂent conÂstrucÂtions for the top elecÂtrode have been testÂed. The entire manÂuÂfacÂturÂing process is comÂpleteÂly CMOS comÂpatÂiÂble, which along with the low device proÂfile of about 4 μm makes the devices readÂiÂly availÂable for inteÂgraÂtion on a CMOS-chip, in 3D stackÂing, or in a 2.5D interÂposÂer techÂnolÂoÂgy. CapacÂiÂtance valÂues of up to 18.2 nF/​mm2 (per device footÂprint area) are achieved reproducibly.
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