Integrated on-chip solid state capacitor based on vertically aligned nanofibers, grown using a CMOS temperature compatible process

Research paper pub­lished in Solid–State Elec­tron­ics, Vol­ume 139, Jan­u­ary 2018, pp. 75–79.

Com­plete minia­tur­ized on-chip inte­grat­ed sol­id-state capac­i­tors have been fab­ri­cat­ed based on con­for­mal coat­ing of ver­ti­cal­ly aligned car­bon nanofibers (VAC­N­Fs), using a CMOS tem­per­a­ture com­pat­i­ble micro­fab­ri­ca­tion process­es. The 5 µm long VAC­N­Fs, oper­at­ing as elec­trode, are grown on a sil­i­con sub­strate and con­for­mal­ly coat­ed by alu­minum oxide dielec­tric using atom­ic lay­er depo­si­tion (ALD) tech­nique. The are­al (foot­print) capac­i­tance den­si­ty val­ue of 11–15 nF/​mm2 is real­ized with high repro­ducibil­i­ty. The CMOS tem­per­a­ture com­pat­i­ble micro­fab­ri­ca­tion, ultra-low pro­file (less than 7 µm thick­ness) and high capac­i­tance den­si­ty would enables direct inte­gra­tion of micro ener­gy stor­age devices on the active CMOS chip, mul­ti-chip pack­age and pas­sives on sil­i­con or glass inter­pos­er. A mod­el is devel­oped to cal­cu­late the sur­face area of VAC­N­Fs and the effec­tive capac­i­tance from the devices. It is there­by shown that 71 % of sur­face area of the VAC­N­Fs has con­tributed to the mea­sured capac­i­tance, and by using the entire area the capac­i­tance can poten­tial­ly be increased.

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