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Sem Image Of The Cnf Mim Prototype Only 38 Microns Thick

Ultra-thin capacitors

Smol­tek has developed a pro­to­type of the thin­nest dis­crete capa­cit­or in the world. Its total build­ing height is less than 40 micro­met­ers (38.2 µm to be exact). You have to stack a bunch of them on top of each oth­er to reach the same height as today’s industry-stand­ard regard­ing sur­face-moun­ted dis­crete capa­cit­ors. The capa­cit­or, without encap­su­la­tion and sub­strate, is merely 0.5 to 10 µm in height. It can be built dir­ectly onto an integ­rated circuit’s die or built into its interposer.

The most amaz­ing thing about this micro­scop­ic capa­cit­or is its per­form­ance. One square mil­li­meter has a capa­cit­ance of a whop­ping 650 nan­o­farads (650 nF/​mm2). Its intern­al res­ist­ance (ESR) is less than forty mil­liohms (40 mΩ), and its intern­al induct­ance (ESL) is below fif­teen pico­henry (15 pH).

We describe our capa­cit­or as a CNF-MIM capa­cit­or since it is a met­al-insu­lat­or-met­al (MIM) capa­cit­or where car­bon nan­ofibers (CNF) are used to cre­ate a much lar­ger sur­face area, hence high­er capa­cit­ance than the form factor suggests.

Chip with capacitors placed on the underside
The decoup­ling capa­cit­ors are loc­ated on the under­side of the applic­a­tion pro­cessor chip.

We are devel­op­ing ultra-thin and high-per­form­ance nan­ofiber-based capa­cit­ors for mobile applic­a­tion pro­cessors. The driv­ing voltage decreases in today’s pro­cessors because more and more tran­sist­ors can fit on a giv­en sur­face. The lower drive voltage makes the pro­cessors increas­ingly sens­it­ive to inter­fer­ence, and a num­ber of so-called decoup­ling capa­cit­ors are required to sta­bil­ize the power supply.

To increase per­form­ance and reduce power con­sump­tion, these capa­cit­ors must be placed as close to the pro­cessor chip as pos­sible. For the capa­cit­ors to be placed as close to the pro­cessor chip as pos­sible, they must be extremely thin. They must also be high-per­form­ance, i.e. stable at high fre­quen­cies and with low intern­al losses.

Our car­bon nan­o­tech­no­logy makes it pos­sible to man­u­fac­ture capa­cit­ors with a unique com­bin­a­tion of super­i­or elec­tric­al per­form­ance at very high fre­quen­cies and an extremely small form factor—ultra-thin capacitors.

Smoltek’s upcom­ing product fam­ily for decoup­ling capa­cit­ors for the semi­con­duct­or industry is inten­ded to be placed in the applic­a­tion pro­cessor chip.

Technical data—CNF-MIM capacitor technology

  • Sol­id-state construction
  • Capa­cit­ance dens­ity: > 650 nF/​mm2
  • Equi­val­ent series res­ist­ance (ESR): < 40 mΩ
  • Equi­val­ent series induct­ance (ESL): < 15 pH
  • Break­down voltage: Up to ~ 25 V
  • Leak­age cur­rent: ~ 4 mA/​F
  • Excel­lent capa­cit­ance sta­bil­ity up to 150 °C

Applications for discrete CNF-MIM capacitors

A dis­crete CNF-MIM capa­cit­or has a smal­ler foot­print (area) and much thin­ner pro­file (z‑dimension) than any oth­er capa­cit­or with the same capa­cit­ance. CNF-MIM capa­cit­ors up to more than 650 nF can be made less than 40 µm in height. The actu­al form factor can be var­ied accord­ing to the design and need.

As shown in the illus­tra­tions, a dis­crete CNF-MIM capa­cit­or can be

  • moun­ted on prin­ted cir­cuit board (PCB)
  • embed­ded in PCB
  • moun­ted on chip interposer
  • embed­ded in chip interposer
  • moun­ted on chip die
  • Dis­crete CNF-MIM capa­cit­ors are com­pat­ible with wafer-to-wafer (W2W) or die-to-wafer bond­ing (D2W).

Applications for integrated CNF-MIM capacitors

A CNF-MIM capa­cit­or can also be integ­rated dir­ectly into chip die or chip inter­poser. The height of the integ­rated capa­cit­ors is a mere 0.5 to 10 µm. The bene­fits of integ­rated CNF-MIM are many:

  • CMOS-com­pat­ible man­u­fac­tur­ing process
  • Unpar­alleled design free­dom for cir­cuit designers
  • Pos­sible to man­u­fac­ture dir­ectly on-chip
  • Closer to the cir­cuit where it is needed
  • Extremely small 2D footprint
  • Very com­pact 3D volume
  • Elim­in­ates the need for integ­rated dis­crete capacitors

As shown in the illus­tra­tions, a CNF-MIM capa­cit­or can be

  • integ­rated with chip interposer
  • integ­rated with built-on-chip die

Discrete CNF-MIM capacitor compared to alternatives

Mul­tilay­er Ceram­ic Capa­cit­ors (MLCC) form the industry stand­ard for sur­face-moun­ted device (SMD) capa­cit­ors. Every year, tril­lions of MLCCs are built into elec­tron­ic devices. They are 300 µm high. CNF-MIM offers the same capa­cit­ance at a tenth of that height.

The mini­atur­iz­a­tion of elec­tron­ics is cre­at­ing a grow­ing need for ever-smal­ler capa­cit­ors. And some cir­cuits (such as Apple’s) use capa­cit­ors that are state of the art. These use improve­ments of MLCC and Low Induct­ance Chip Capa­cit­ors (LICCs) and Trench Sil­ic­on Capa­cit­ors (TSCs), all of which have a height of 80–100 µm.

How­ever, MLCC, LICC, and TSC struggle to go down in height due to mater­i­als involved, pro­cessing schemes, and the cost of raw mater­i­als and pro­cessing. At the same time, SiP and SoC con­tin­ue to become more com­pact. There is less and less space between inter­con­nects (bumps), and they are get­ting short­er. To fit capa­cit­ors between the bumps, the capa­cit­ors must have a smal­ler foot­print and, above all, be shorter—preferably less than 20 µm.

This is the prob­lem that CNF-MIM capa­cit­ors solve. They have a much smal­ler foot­print and, above all, a much lower height.

How to make the world’s thinnest capacitor

To cre­ate a capa­cit­or with a min­im­al foot­print and height, we use car­bon nan­ofibers (CNFs) to mul­tiply the con­tact area between the two metals and the inter­me­di­ary dielectric.

Con­sider a single CNF with a dia­met­er of 10 nm and a length of 5 µm. Its mantle sur­face is 2,000 times lar­ger than the area it occu­pies. Thus, a forest of such CNFs would mul­tiply the sur­face, but not by as much as 2,000. We can’t cov­er the entire ori­gin­al sur­face with CNFs; there must be space between them to allow access to the con­tact sur­face. But if the forest of CNFs cov­ers about half the sur­face, then the sur­face mul­ti­plic­a­tion would be in the range of 1,000 times.

Car­bon nan­ofiber met­al-insu­lat­or-met­al capacitor.

CNF has many metal­lic prop­er­ties, includ­ing being a good con­duct­or of cur­rent. There­fore a met­al plate covered to fifty per­cent by CNFs is a single elec­trode with a sur­face area about 1,000 times lar­ger than the area of the met­al plate itself. A MIM capa­cit­or is obtained by coat­ing this elec­trode with a uni­formly thick lay­er of a dielec­tric and then coat­ing this in turn with a met­al. Of course, the dielec­tric should have a high rel­at­ive per­mit­tiv­ity to max­im­ize the capacitance.

Since the CNF has a length much lar­ger than the dia­met­er, we can neg­lect what hap­pens to the elec­tric field near the base and top of each CNF. Essen­tially it will be a uni­form field, just as in a par­al­lel plate capacitor.

Since the capa­cit­ance of a par­al­lel plate capa­cit­or is dir­ectly pro­por­tion­al to the sur­face area, we con­clude that CNFs have increased the capa­cit­ance dens­ity by 1,000 times.

But it doesn’t end there. If the second lay­er of met­al is made uni­formly thick, both sides of it will have the same shape as the first elec­trode. So anoth­er MIM capa­cit­or is obtained by coat­ing it with anoth­er dielec­tric lay­er and then coat­ing it with met­al. It will have the same capa­city as the first. And by elec­tric­ally con­nect­ing the first and the third met­al lay­er, we achieve a par­al­lel con­nec­tion, which doubles the capa­cit­ance. This can be repeated as long as desired, and there is space between the car­bon nan­ofibers. The last lay­er of met­al does not need to be uni­formly thick but can fill any remain­ing spaces between the car­bon nanofibers.

Learn more

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