The case for CNF-MIM in next-generation AI power delivery

Mod­ern AI proces­sors do not only need more pow­er. They need pow­er deliv­ered at very high cur­rent and with extreme­ly fast tran­sient response. That com­bi­na­tion cre­ates a bru­tal engi­neer­ing prob­lem. At a core rail below 1 V, a 700 W accel­er­a­tor cor­re­sponds to hun­dreds of amps of cur­rent. If we assume a 0.8 V rail, the cur­rent is approx­i­mate­ly 875 A.

At that lev­el, tiny par­a­sitics are no longer tiny. A resis­tance of only 0.1 mΩ cre­ates an 87.5 mV volt­age drop. A loop induc­tance of only 10 pH exposed to a 10 A/​ns cur­rent tran­sient cre­ates a 100 mV volt­age dis­tur­bance. These num­bers are large com­pared with the avail­able volt­age mar­gin on a sub‑1 V rail. 

This is why pow­er deliv­ery has become one of the defin­ing chal­lenges in AI and HPC hard­ware, with capac­i­tors play­ing a cen­tral role in deter­min­ing sys­tem per­for­mance, effi­cien­cy, and reliability.

Lateral power delivery—the current solution based on MLCCs

The first gen­er­a­tion of high-pow­er accel­er­a­tor boards large­ly fol­lowed the same log­ic used in servers and graph­ics cards for many years. Volt­age reg­u­la­tors, induc­tors and capac­i­tors were placed around the proces­sor or accel­er­a­tor pack­age. Pow­er was con­vert­ed on the board and then rout­ed lat­er­al­ly across the PCB and pack­age to reach the silicon. 

This approach is prac­ti­cal and famil­iar. It uses mature mul­ti­phase volt­age-reg­u­la­tor mod­ules, proven PCB man­u­fac­tur­ing and a large ecosys­tem of dis­crete mul­ti­lay­er ceram­ic capac­i­tors (MLCCs) and induc­tors. Look­ing at AI accel­er­a­tor boards such as the NVIDIA H100 gen­er­a­tion, the basic archi­tec­ture is still rec­og­niz­able: high-pow­er inputs, board-lev­el con­ver­sion and dense clus­ters of pow­er com­po­nents around the main package. 

For the H100 SXM form fac­tor, NVIDIA spec­i­fies a ther­mal design pow­er of up to 700 W. The PCIe ver­sion is low­er pow­er, but still rep­re­sents a very high-cur­rent pow­er-deliv­ery chal­lenge. The impor­tant point is not only the absolute pow­er. It is the fact that this pow­er must ulti­mate­ly be deliv­ered to low-volt­age rails close to the die. 

Lat­er­al pow­er deliv­ery works, but it scales poor­ly as cur­rent ris­es. A capac­i­tor can only sup­port fast tran­sients effec­tive­ly if the path between the capac­i­tor and the load has very low resis­tance and imped­ance. When the capac­i­tor is placed too far away, as is the case in lat­er­al pow­er deliv­ery, the added resis­tance and induc­tance slow down its response and reduce its abil­i­ty to deliv­er charge exact­ly when the proces­sor needs it. The result is high­er volt­age droop, more sup­ply noise, reduced pow­er effi­cien­cy and a grow­ing need for capac­i­tors that can be placed much clos­er to the die.

This is the first major open­ing for ultra-thin capac­i­tors. Thanks to their very low-pro­file form fac­tor, they enable decou­pling to move much clos­er to the point of load — some­thing that is not real­is­ti­cal­ly pos­si­ble with con­ven­tion­al MLCC banks. 

Vertical power delivery—the need for ultra-thin capacitors

Instead of rout­ing high cur­rent side­ways across the board, com­pact pow­er mod­ules can be placed under­neath the proces­sor and push pow­er ver­ti­cal­ly upward through the board and pack­age. This short­ens the high-cur­rent path, reduces con­duc­tion loss and improves pow­er integri­ty. This is a major improve­ment for AI and HPC proces­sors because it attacks the two key prob­lems at once: resis­tance and induc­tance.
To pre­serve the ben­e­fit of this archi­tec­ture, decou­pling capac­i­tors must also move clos­er to the point of load, often into spaces where con­ven­tion­al capac­i­tor banks can­not fit. This requires capac­i­tors that are not only extreme­ly thin, but also capa­ble of deliv­er­ing low ESR, low ESL and high capac­i­tance den­si­ty in a very small vol­ume. That com­bi­na­tion makes ultra-thin capac­i­tors a key enabling tech­nol­o­gy for ver­ti­cal pow­er delivery.

How­ev­er, tra­di­tion­al capac­i­tor tech­nolo­gies have dif­fi­cul­ties deliv­er­ing high enough per­for­mance in a small enough form factor.

Ultra-thin capacitor technologies

At its most fun­da­men­tal lev­el, a capac­i­tor is a sim­ple device: two con­duc­tive elec­trodes sep­a­rat­ed by an insu­lat­ing dielec­tric. The more elec­trode sur­face area that can be packed into a giv­en vol­ume, the more capac­i­tance can be achieved in that same footprint.

This is why the geom­e­try of the elec­trode struc­ture mat­ters so much. For con­ven­tion­al pla­nar capac­i­tors, the avail­able sur­face area is lim­it­ed by the foot­print of the device. To increase capac­i­tance den­si­ty, the indus­try has there­fore moved toward three-dimen­sion­al struc­tures that increase the effec­tive elec­trode area with­out increas­ing the foot­print of the component.

There are two main ways to do this:

1. The first approach is sub­trac­tive: start with a sil­i­con sub­strate and etch deep, nar­row holes or trench­es into it. A dielec­tric and elec­trode stack is then deposit­ed into the trench­es, form­ing what is known as a deep trench capac­i­tor (DTC). This is a pow­er­ful con­cept and has enabled thin sil­i­con capacitors.
2. The sec­ond approach is addi­tive: instead of dig­ging sur­face area into the sub­strate, build high-sur­face-area struc­tures on top of it. 

This is the prin­ci­ple behind Smoltek’s pro­pri­etary car­bon nanofiber-based met­al-insu­la­tor-met­al (CNF-MIM) tech­nol­o­gy. Smoltek grows ver­ti­cal­ly aligned car­bon nanofibers from the sur­face, cre­at­ing a dense for­est of con­duc­tive nanos­truc­tures with extreme­ly high aspect ratio. These car­bon nanofibers dra­mat­i­cal­ly increase the avail­able elec­trode sur­face area with­in a very small vol­ume. A con­for­mal dielec­tric lay­er is then deposit­ed around the nanofibers, fol­lowed by the top elec­trode, form­ing a met­al-insu­la­tor-met­al capac­i­tor in a three-dimen­sion­al nanos­truc­tured geometry. 

One key dif­fer­ence between CNF-MIM and deep trench capac­i­tors is the aspect ratio of the under­ly­ing 3D struc­ture that cre­ates the capac­i­tor sur­face area. In DTC tech­nol­o­gy, the sur­face gain comes from trench­es etched into sil­i­con result­ing in aspect ratios typ­i­cal­ly below 25. In Smoltek’s CNF-MIM tech­nol­o­gy, the 3D struc­ture is instead formed by ver­ti­cal­ly aligned car­bon nanofibers with an aver­age diam­e­ter of less than 100 nm result­ing aspect ratios of exceed­ing 100 (see Fig­ure 4). This much high­er aspect ratio means that CNF-MIM can gen­er­ate sig­nif­i­cant­ly more elec­trode sur­face area in the same volume. 

The high­er aspect ratio of CNF-MIM also trans­lates direct­ly into a cost advan­tage. Because deep trench capac­i­tors have a low­er aspect ratio, they often need to com­pen­sate by deposit­ing mul­ti­ple met­al-insu­la­tor-met­al stacks inside the trench­es to reach high capac­i­tance den­si­ty. Each addi­tion­al elec­trode and dielec­tric lay­er adds process com­plex­i­ty and increas­es the fab­ri­ca­tion cost, espe­cial­ly because these films are typ­i­cal­ly deposit­ed using low-through­put ALD process­es. CNF-MIM, by con­trast, can achieve high capac­i­tance den­si­ty with a sin­gle dielec­tric stack coat­ed con­for­mal­ly over the car­bon nanofibers. 

In addi­tion, DTC requires high-res­o­lu­tion lith­o­g­ra­phy to define dense and nar­row trench struc­tures, while CNF-MIM nanofibers can be grown from cat­a­lyst nanopar­ti­cles formed by dewet­ting of a con­tin­u­ous cat­a­lyst film. This elim­i­nates the need for cost­ly high-res­o­lu­tion lith­o­g­ra­phy and gives CNF-MIM a sim­pler and cheap­er route to high capac­i­tance density.

Anoth­er impor­tant advan­tage of CNF-MIM is that it is sub­strate agnos­tic. In deep trench capac­i­tors, the sil­i­con sub­strate is an inte­gral part of the device because the capac­i­tor sur­face area is cre­at­ed by etch­ing trench­es into the sil­i­con. This makes the tech­nol­o­gy inher­ent­ly tied to sil­i­con and lim­its its trans­fer­abil­i­ty to oth­er sub­strate plat­forms. In con­trast car­bon nanofibers are grown on top of the substrate. 

In fact, Smoltek has already demon­strat­ed CNF growth on a vari­ety of mate­ri­als, includ­ing sil­i­con, glass, alu­mi­na, stain­less steel foil, cop­per foil and alu­minum foil. This flex­i­bil­i­ty is strate­gi­cal­ly impor­tant because future pow­er-deliv­ery archi­tec­tures will not be lim­it­ed to sil­i­con alone. 

For exam­ple, glass sub­strates are gain­ing inter­est for advanced inter­posers because of their dimen­sion­al sta­bil­i­ty, fine-line rout­ing poten­tial and suit­abil­i­ty for large-area pan­el-lev­el integration. 

A capac­i­tor tech­nol­o­gy that can be imple­ment­ed on glass offers a broad­er inte­gra­tion path for advanced pack­ag­ing, embed­ded capac­i­tance and ver­ti­cal pow­er-deliv­ery solutions.

Integrated power delivery—the future direction with CNF-MIM

The next step is to move the volt­age reg­u­la­tion even clos­er to the point of load. 

Inte­grat­ed volt­age reg­u­la­tors and com­pact pow­er-con­vert­er chiplets are part of this trend. Instead of plac­ing the reg­u­la­tor only on the board, future archi­tec­tures may place pow­er con­ver­sion on the land side of the pack­age, inside the pack­age sub­strate, or close to the die itself. The objec­tive is clear: reduce the dis­tance between the reg­u­la­tor, the decou­pling capac­i­tor and the load. 

This is a log­i­cal con­tin­u­a­tion of the same trend. Lat­er­al pow­er deliv­ery placed pow­er around the proces­sor. Ver­ti­cal pow­er deliv­ery moved pow­er under­neath the proces­sor. Pack­age-lev­el and inte­grat­ed pow­er deliv­ery bring con­ver­sion and decou­pling even clos­er to the point of load. At that point, thick­ness becomes the crit­i­cal dif­fer­en­tia­tor. This is where CNF-MIM has a deci­sive advan­tage over DTC: it can be made thinner. 

In deep trench capac­i­tors, the sil­i­con sub­strate is not just a car­ri­er; it is part of the capac­i­tor itself because the trench­es are etched into it. This lim­its how aggres­sive­ly the wafer can be thinned with­out com­pro­mis­ing the device. CNF-MIM is fun­da­men­tal­ly dif­fer­ent. The ultra-thin active capac­i­tor struc­ture is built addi­tive­ly on top of the sub­strate, while the sub­strate main­ly serves as a car­ri­er. This allows much more aggres­sive thin­ning and enables final devices as thin as 40 µm, com­pared with rough­ly 100 µm for typ­i­cal DTC solutions. 

More­over, the ultra-thin active capac­i­tor lay­er can be formed direct­ly on sub­strates that are already very thin, such as met­al foils or oth­er flex­i­ble car­ri­er mate­ri­als. Instead of rely­ing on a thick sil­i­con wafer that must lat­er be etched and thinned, CNF-MIM can in prin­ci­ple be built where the final form fac­tor is defined pri­mar­i­ly by the start­ing sub­strate and the few-microm­e­ter-thick active layer.

Summary

First, CNF-MIM offers a more attrac­tive path to cost-effi­cient high capac­i­tance den­si­ty. Deep trench capac­i­tors cre­ate sur­face area by etch­ing nar­row struc­tures into sil­i­con, which requires demand­ing lith­o­g­ra­phy and deep sil­i­con pro­cess­ing. Because the trench aspect ratio is lim­it­ed, DTC tech­nol­o­gy often needs mul­ti­ple met­al-insu­la­tor-met­al stacks to com­pen­sate and reach high capac­i­tance den­si­ty. That adds process com­plex­i­ty, ALD time and cost. CNF-MIM takes a dif­fer­ent route. It cre­ates high sur­face area addi­tive­ly, by grow­ing car­bon nanofibers from the sur­face, and can achieve high capac­i­tance den­si­ty with a sin­gle con­for­mal dielec­tric stack. This makes CNF-MIM not only tech­ni­cal­ly dif­fer­ent, but poten­tial­ly sim­pler and cheap­er to manufacture. 

Sec­ond, CNF-MIM is not locked to sil­i­con. This is strate­gi­cal­ly impor­tant. Since the active nanofiber struc­ture is grown on top of the sub­strate, the same basic con­cept can be trans­ferred to dif­fer­ent car­ri­er mate­ri­als, includ­ing glass, alu­mi­na, stain­less steel, cop­per and alu­minum. Glass is espe­cial­ly impor­tant for the future of advanced pack­ag­ing and scal­able inte­gra­tion, where large-area pro­cess­ing, dimen­sion­al sta­bil­i­ty and fine-line rout­ing are becom­ing increas­ing­ly attrac­tive. A capac­i­tor tech­nol­o­gy that can move beyond sil­i­con and fol­low the indus­try toward new pack­age and inter­pos­er plat­forms has a much stronger long-term inte­gra­tion path. 

But the most impor­tant advan­tage is thick­ness. Future pow­er deliv­ery is mov­ing from the board to under­neath the proces­sor, to the pack­age, and even­tu­al­ly as close as pos­si­ble to the sil­i­con itself. In that world, every microm­e­ter mat­ters. A capac­i­tor is no longer use­ful only because it has high capac­i­tance den­si­ty; it must also fit into extreme­ly lim­it­ed ver­ti­cal space. This is where CNF-MIM wins most clear­ly. In DTC, the sil­i­con sub­strate is part of the capac­i­tor struc­ture itself, because the trench­es are etched into it. That lim­its how far the device can be thinned. In CNF-MIM, the active capac­i­tor is built addi­tive­ly on top of the sub­strate, while the sub­strate main­ly acts as a car­ri­er. This makes much more aggres­sive thin­ning pos­si­ble and enables devices down to around 40 µm. 

This com­bi­na­tion is what makes CNF-MIM such a strong can­di­date for the next gen­er­a­tion of ultra-thin decou­pling capac­i­tors. It offers a poten­tial­ly low­er-cost route to high capac­i­tance den­si­ty, it can be inte­grat­ed into future-rel­e­vant sub­strates such as glass, and above all, it can be made extreme­ly thin. As pow­er deliv­ery moves clos­er to the proces­sor, that thick­ness advan­tage becomes decisive.

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