Carbon nanofibers in the semiconductor industry

With our car­bon nanofibers (CNFs) fab­ri­ca­tion tech­nol­o­gy, we devel­op advanced pack­ing solu­tions and ultra-minia­tur­ized capac­i­tors for use in the semi­con­duc­tor industry.

Based on our CNF-tech­nol­o­gy, we have devel­oped an assem­bly plat­form that push­es the lim­its for het­ero­ge­neous inte­gra­tion in 2.5D and 3D. The plat­form offers ultra-fine pitch microbumps, ultra thin ther­mal film for heat dis­si­pa­tion, ultra minia­tur­ized capac­i­tors inte­grat­ed direct­ly onto dies or embed­ded into inter­posers, and an inter­pos­er with built-in DC stor­age smooth­ing out vari­a­tions in pow­er supply.

Ultra-fine pitch microbumps made of car­bon nanofibers.
Close-up of a wafer with Smoltek’s car­bon nanofiber met­al-insu­la­tor-met­al (CNF-MIM) capacitor—the world’s thinnest capacitor.

We have also devel­oped the world’s small­est capac­i­tor. The total height is only 30 µm—which is less than half what is pos­si­ble with oth­er tech­nolo­gies. Its capac­i­tance is a whop­ping 650 nF/​mm2. Its inter­nal resis­tance (ESR) is less than 40 mΩ, and its inter­nal induc­tance (ESL) is below 15 pH.

We offer a tech­ni­cal part­ner­ship to man­u­fac­tur­ers who want to devel­op their offer in het­ero­ge­neous inte­gra­tion or pas­sive com­po­nents with our tech­nol­o­gy to short­en devel­op­ment time and min­i­mize risks. Are you inter­est­ed? Con­tact us now to learn more.

Smoltek team mem­bers in the lab.

What are semiconductors?

A mate­r­i­al is an elec­tri­cal con­duc­tor if an elec­tric field can move an elec­tron from one atom to the next. Only the elec­tron in the out­er­most shell around an atom­ic nucle­us can do that, and only if there is an even fur­ther out shell that it can jump to with ener­gy from the elec­tric field.

If the dis­tance between the out­er­most shell of elec­trons and the next shell is too great for elec­trons to jump out there, the sub­stance is an elec­tri­cal insu­la­tor.

For some mate­ri­als, such as sil­i­con, the gap is so small that some elec­trons can jump across the gap. When the elec­tron cross­es the gap, it leaves behind a hole. Under the influ­ence of an elec­tri­cal field, both the elec­tron and the hole can move across the mate­r­i­al. It con­ducts elec­tric­i­ty, but poor­ly. That’s why such a sub­stance is called semi­con­duc­tor.

The con­duc­tiv­i­ty can be dra­mat­i­cal­ly improved by adding impu­ri­ties in the form of oth­er sub­stances that add extra elec­trons or holes. This is called n‑doping and p‑doping, respec­tive­ly.

The magic at the p‑n-junction

A p‑n-junc­tion is where p‑doped semi­con­duc­tor meets n‑doped semi­con­duc­tor. At p‑n-junc­tions, the mag­ic hap­pens that makes mod­ern elec­tron­ics possible.

Because there is an excess of elec­trons in the n‑doped semi­con­duc­tor and a deficit of elec­trons (holes) in the p‑doped semi­con­duc­tor, elec­trons dif­fuse from the n‑doped to the p‑doped semi­con­duc­tor to reach equi­lib­ri­um. This cre­ates a region that is deplet­ed of elec­trons and holes that can car­ry cur­rent. Con­se­quent­ly, the region is said to be a deple­tion region.

By apply­ing a volt­age across the p‑n junc­tion one can cause the deple­tion region to increase (which blocks cur­rent from pass­ing) or decrease (which allows cur­rent to pass). This is what is exploit­ed in transistors.

How transistors work

A tran­sis­tor acts like an elec­tri­cal­ly con­trolled tap. By gen­tly turn­ing the tap, more or less flow can be cre­at­ed. This fea­ture is used in ana­log elec­tron­ics to ampli­fy sig­nals. By quick­ly turn­ing the tap on or off, “ones and zeros” are cre­at­ed in terms of cur­rent pass­ing or not. This is the foun­da­tion of all dig­i­tal elec­tron­ics, not least computers.

The first tran­sis­tor was cre­at­ed in Decem­ber 1947 at the Bell Tele­phone Lab­o­ra­to­ries. A cou­ple of years lat­er, what we today think of as a tran­sis­tor was invent­ed. It con­sists of n‑doped or p‑doped semi­con­duc­tors through which cur­rent is passed. The mid­dle part of the semi­con­duc­tor is replaced by a piece of semi­con­duc­tor of the oppo­site type. It cre­ates two p‑n junc­tions. By sup­ply­ing cur­rent through the mid­dle sec­tion, the width of the two deple­tion regions can be changed. Thus, a cur­rent through the mid­dle sec­tion con­trols how much of the cur­rent through the tran­sis­tor is allowed to pass. Since both neg­a­tive and pos­i­tive charges are mov­ing (elec­trons and elec­tron holes, respec­tive­ly), it is called bipo­lar junc­tion tran­sis­tor (BJT).


A tran­sis­tor con­trolled by an elec­tric field instead of cur­rent is called a field-effect tran­sis­tor (FET). While the BJT always con­sumes pow­er, the FET con­sumes no pow­er when its tap is unchanged (e.g., on or off). That’s per­fect for cre­at­ing ener­gy-effi­cient dig­i­tal electronics.

The first field-effect tran­sis­tor was devel­oped in 1953. But it had prob­lems with leak­ag­ing cur­rent where p–n junc­tions inter­cept the surface.

In the late 1950s, Mohamed M. Atal­la of Bell Tele­phone Lab­o­ra­to­ries dis­cov­ered that a thin lay­er of insu­lat­ing sil­i­con diox­ide on top of a semi­con­duc­tor pre­vents leak­age cur­rent. But how to make elec­tric con­tact with a FET if an insu­lat­ing lay­er cov­ers its surface?

Mohamed M. Atal­la and his col­league Dawon Kah­ng ele­gant­ly solved this. They added met­al gates on top of the oxide lay­er where they want­ed the con­nec­tion. The stack of met­al, oxide, and semi­con­duc­tor form a par­al­lel-plate capac­i­tor. The met­al gate is one elec­trode, the semi­con­duc­tor under­neath is the oth­er elec­trode, and the thin sil­i­con diox­ide lay­er acts as the dielec­tric. The much improved FET was named met­al-oxide-semi­con­duc­tor field-effect tran­sis­tor, or MOSFET for short.

One of the MOS­FETs’ many ben­e­fits is that com­pared to BJTs they are rel­a­tive­ly easy to pro­duce. There­fore, it is bet­ter to use MOS­FETs in inte­grat­ed cir­cuits. Dawon Kah­ng point­ed this out in 1961.

Integrated circuit (IC)—chip

An inte­grat­ed cir­cuit (IC) is a set of elec­tron­ic cir­cuits on one small flat piece of semi­con­duc­tor called chip. The idea of com­bin­ing sev­er­al com­po­nents in one device goes back to 1949. But it wasn’t until a decade lat­er that the first IC in a mod­ern sense was fab­ri­cat­ed. It used bipo­lar junc­tion tran­sis­tors (BJT). The first chip with MOSFET was fab­ri­cat­ed in 1961.

MOS­FETs are supe­ri­or to BJTs in inte­grat­ed cir­cuits because they are eas­i­er to pro­duce and can be made much small­er. It took only two years after the first MOSFET chip was pro­duced before chips with MOSFET reached high­er tran­sis­tor den­si­ty and low­er man­u­fac­tur­ing costs than those with BJTs.


In the late 1960s, the com­ple­men­tary met­al-oxide-semi­con­duc­tor (CMOS) was devel­oped. The name refers to both a par­tic­u­lar style of dig­i­tal cir­cuit­ry design, cre­at­ing dig­i­tal gates by com­bin­ing two MOS­FETs of oppo­site dop­ing, and a process used to imple­ment that cir­cuit­ry on inte­grat­ed cir­cuits (chips). Two impor­tant char­ac­ter­is­tics of CMOS devices are high noise immu­ni­ty and low sta­t­ic pow­er consumption.

Chip manufacturing process

The pro­duc­tion of chips is a com­plex process that can take up to three months. Today, they are usu­al­ly man­u­fac­tured accord­ing to the fol­low­ing steps:

  1. Extreme­ly pure sil­i­cone is pro­duced from quartzite or sand. The sil­i­cone is shaped into a cylin­dri­cal ingot with a diam­e­ter of up to 300 mil­lime­ters. The sil­i­con ingot is then sliced into discs; each disc is 0.75 mil­lime­ters thick and is called a wafer.
  2. Sev­er­al thin lay­ers of insu­lat­ing, semi­con­duct­ing, and con­duct­ing mate­ri­als are placed on a wafer. Which mate­ri­als and in what order depends on what is to be pro­duced. This is called depo­si­tion.
  3. The last lay­er applied is a pho­tore­sist—a sub­stance resis­tant to cor­ro­sive sub­stances except where it has been exposed to ultra­vi­o­let light.
  4. The next step is lith­o­g­ra­phy. Deep ultra­vi­o­let (DUV) or extreme ultra­vi­o­let (EUV) light is sent through a ret­i­cle with the draw­ing of the pat­tern to be cre­at­ed. Lens­es or mir­rors are used to shrink and focus the pat­tern pro­ject­ed onto the pho­tore­sist. Where the light hits the pho­tore­sist, it los­es its resis­tance to cor­ro­sive sub­stances, while the resis­tance remains where the light has not hit.
  5. Wafers are now placed in a chem­i­cal bath that erodes exposed pho­tore­sist while leav­ing the unex­posed pho­tore­sist unaf­fect­ed. This is called wet etch­ing. Instead of a bath, gas can also be used. This is called dry etch­ing. The result is that under­ly­ing lay­ers are uncov­ered where the light has hit while the rest is still shielded.
  6. Once pat­terns are etched in the wafer, the wafer may be bom­bard­ed with pos­i­tive or neg­a­tive ions to dope uncov­ered semi­con­duc­tors. This is called ion implan­ta­tion.
  7. Now, the remain­ing sec­tions of resist that were pro­tect­ing areas that should not be etched or ion­ized are removed.
  8. Steps 2–7 are repeat­ed repeat­ed­ly until the desired func­tion­al­i­ty is achieved. Mod­ern chips can have up to two hun­dred lay­ers, which all need to align on top of each oth­er with extreme precision.
  9. A wafer holds cir­cuits for many chips. How many cir­cuits depends on how large they are. Some wafers may con­tain thou­sands of cir­cuits, while oth­ers con­tain only a few dozen. The cir­cuits are cut out with a dia­mond saw. The cut-out pieces of the wafer are called dies.
  10. The chip is now cre­at­ed by mount­ing the die on a sub­strate that acts as a back­plane with con­nect­ing wires.
  11. Final­ly, the chip is put into a plas­tic pack­age with con­nect­ing pins.
Sil­i­con wafer after the dic­ing process.

Minimum costs per transistor

Although chip man­u­fac­tur­ing has been refined since the first MOSFET chips were pro­duced, not all dies will work. There­fore, each die must be test­ed (which is typ­i­cal­ly done before the wafer is diced). The per­cent­age that pass­es is called the die yield.

The cost per tran­sis­tor decreas­es with the num­ber of tran­sis­tors that fit on a chip to a point where the cost increas­es again due to decreas­ing yield. Thus there is an inflec­tion point where the cost per tran­sis­tor is the low­est possible.

In an arti­cle pub­lished in 1965 in Elec­tron­ics (Vol­ume 38, Num­ber 8), Gor­don E. Moore—co-founder of Fairchild Semi­con­duc­tor and lat­er Intel—referred to this opti­mal point as “min­i­mum com­po­nent costs.” More­over, he not­ed that in those few years that chips had been pro­duced, the num­ber of tran­sis­tors giv­ing min­i­mum com­po­nent costs had dou­bled each year. He pre­dict­ed that this growth rate would con­tin­ue for anoth­er ten years.

Moore’s law

When he looked back at his pre­dic­tion in 1975, Moore, who now was CEO of Intel, found it was almost spot on. Instead of an expect­ed increase of 210, the increase was 29. In oth­er words, the num­ber of tran­sis­tors at the low­est price point dou­bled every 13 months.

At the 1975 IEEE Inter­na­tion­al Elec­tron Devices Meet­ing, Moore revised his fore­cast rate, pre­dict­ing that semi­con­duc­tor com­plex­i­ty would con­tin­ue to dou­ble annu­al­ly until about 1980, after which it would decrease to a rate of dou­bling approx­i­mate­ly every two years.

One of Moore’s friends, Dr. Carv­er Mead, a pro­fes­sor at Cal­tech, dubbed this revised pre­dic­tion as Moore’s Law.

House’s postulate

In a sci­en­tif­ic paper pub­lished in 1974, the pow­er con­sump­tion of MOS­FETs was shown to decrease lin­ear­ly with the area they occu­py. This rela­tion­ship is called Den­nard scal­ing.

Dennard’s scal­ing makes it pos­si­ble to dou­ble the num­ber of tran­sis­tors with­out using more pow­er. And if no more pow­er is sup­plied, no more heat needs to be dis­si­pat­ed. Thus it is pos­si­ble to dou­ble the com­pu­ta­tion­al capac­i­ty by dou­bling the num­ber of tran­sis­tors with­out heat dis­si­pa­tion becom­ing a grow­ing prob­lem. This leaves room to increase the clock fre­quen­cy that sets the rate at which ones and zeros are turned off and on.

David House, an Intel exec­u­tive, real­ized that this and oth­er improve­ments make it pos­si­ble to increase com­put­ing capac­i­ty faster than the num­ber of tran­sis­tors. He, there­fore, pos­tu­lat­ed that the per­for­mance of a com­put­er chip dou­bles every eigh­teen months.

House’s pos­tu­lates are often mis­tak­en as Moore’s Law. But these are two sep­a­rate pre­dic­tions, albeit close­ly related.

Is Moore’s law still applicable?

Does Moore’s law still apply? No, not as orig­i­nal­ly for­mu­lat­ed. Den­si­ty at min­i­mum cost per tran­sis­tor has long ceased to dou­ble every two years. How­ev­er, den­si­ty at any cost per tran­sis­tor still dou­bles every two years.

But even this more gen­er­ous inter­pre­ta­tion of Moore’s law will not last for­ev­er. Many indus­try experts believe that Moore’s law will cease to apply alto­geth­er as ear­ly as 2025.

Rea­sons for Moore’s law to cease are many. Obvi­ous­ly, tran­sis­tors can­not become small­er than the atoms that make them up. But even before that, prob­lems arise with quan­tum tun­nel­ing, where elec­trons jump through bar­ri­ers and cause cur­rent leak­age. Anoth­er prob­lem, which is already real, is par­a­sitic tran­sis­tors that cre­ate cir­cuits that shouldn’t be there.

Does it matter?

Does it mat­ter that Moore’s law is com­ing to an end? Not per se, but its impli­ca­tions are profound.

The devel­op­ment of the Inter­net of Things (IoT), self-dri­ving cars, con­nect­ed homes, Vir­tu­al Real­i­ty (VR), and Arti­fi­cial Intel­li­gence (AI) increas­ing­ly demands high com­put­ing capac­i­ty in a small foot­print and at low pow­er con­sump­tion. For this devel­op­ment not to come to a halt with Moore’s law, oth­er solu­tions are need­ed than cram­ming more and more tran­sis­tors onto the same surface.

A fore­cast of what will hap­pen when Moore’s Law ceas­es to apply was giv­en to the semi­con­duc­tor indus­try around 2006 when Den­nard scal­ing broke down.

Breakdown of Dennard scaling

The pow­er con­sump­tion of CMOS cir­cuits is pro­por­tion­al to the clock fre­quen­cy. His­tor­i­cal­ly, the tran­sis­tor pow­er reduc­tion afford­ed by Den­nard scal­ing allowed man­u­fac­tur­ers to raise clock fre­quen­cies from one gen­er­a­tion to the next with­out sig­nif­i­cant­ly increas­ing over­all cir­cuit pow­er consumption.

But around 2006, tran­sis­tors had shrunk­en so much the pow­er required to run them increased due to cur­rent leak­age. Increased pow­er con­sump­tion leads to increased heat gen­er­a­tion. And increased heat caus­es elec­trons to become more mobile, which can cause tran­sis­tors to turn on or off spon­ta­neous­ly, lead­ing to fatal fail­ures. Increased heat also increas­es leak­age cur­rent, which fur­ther increas­es pow­er con­sump­tion and the prob­lems that fol­low. In the worst case, this self-ampli­fi­ca­tion can lead to ther­mal runaway.

Overcoming the Dennard scaling breakdown

The break­down of Den­nard scal­ing prompt­ed a prob­lem that could only be par­tial­ly over­come with improved cool­ing. In the end, it was not rea­son­able to con­tin­ue increas­ing the clock speed. That’s why the clock fre­quen­cy of today’s micro­proces­sors is the same as fif­teen years ago. But the per­for­mance has increased any­way. How?

The solu­tion to over­come the break­down of Den­nard scal­ing was mul­ti-core proces­sors. Instead of increas­ing the speed at which a sin­gle pro­cess­ing unit exe­cut­ed instruc­tions, more units were added. These units, called cores, can work inde­pen­dent­ly with par­al­lel tasks. This increas­es the over­all per­for­mance of the processor.

The solu­tion when Moore’s law breaks down is kind of similar.

System-in-Package (SiP)

The final step in fab­ri­cat­ing inte­grat­ed cir­cuits is to place the chip into a plas­tic pack­age with con­nect­ing pins. In the begin­ning, each such pack­age con­tained only one chip. Even­tu­al­ly, two or more chips began to be placed in the same pack­age to cope with

  • reduced sur­face area due to more and more to be packed into less and less space,
  • reduced yield due to larg­er dies,
  • lim­it­ed trans­mis­sion speed due to capac­i­tance in long wires, and
  • pow­er loss­es due to par­a­sitic capac­i­tance in long wires.

It also allows the assem­bly of sim­pler chips into more com­plex solutions—like Lego. Last­ly, it enables a mix of chips with incom­pat­i­ble man­u­fac­tur­ing and pas­sive com­po­nents (e.g. condensers).

This approach is called het­ero­ge­neous inte­gra­tion, and the result is called a Sys­tem-in-Pack­age or SiP for short.


The eas­i­est way is to assem­ble a SiP is to place two or more dies next to each oth­er on the same sub­strate. The dies are inter­con­nect­ed with each oth­er through wires in the sub­strate. The sub­strate also pro­vides an exter­nal con­nec­tion through tiny globes of solder—called sol­der bumps.

A die can be mount­ed face up. Then the die is con­nect­ed to the inter­con­nec­tions and the sol­der bumps with wires.

More com­mon is to mount a die face down. In this case, the die itself has micro­scop­ic sol­der globes—called microbumps—that come into con­tact with pads on the top of the sub­strate. These pads are, in turn, con­nect­ed to the substrate’s inter­con­nec­tions and sol­der bumps.

This form of SiP is called 2D IC (two-dimen­sion­al inte­grat­ed cir­cuit) because the dies are mount­ed in a sin­gle plane. It is also known as mul­ti-chip mod­ule (MCM).

2.5D IC

The next step up in SiP-com­plex­i­ty is called 2.5D IC (two and a half-dimen­sion­al inte­grat­ed cir­cuit). The name comes from the fact that dies are still side by side, but now face down on an inter­me­di­ate lay­er of silicon—called inter­pos­er. An inter­pos­er has pads on its top and microbumps on its bot­tom. Hor­i­zon­tal elec­tri­cal con­nec­tions inside the sil­i­con inter­con­nect some pads. Some are con­nect­ed to microbumps by a ver­ti­cal elec­tri­cal con­nec­tion run­ning through the silicon—called through sil­i­con via or TSV for short.

So what’s the point of adding an inter­pos­er? An inter­pos­er gen­er­al­ly reroutes con­nec­tions from one con­fig­u­ra­tion and pitch to anoth­er con­fig­u­ra­tion and pitch. But this is not the pri­ma­ry rea­son for their use in 2.5D ICs; the same goal can be achieved with wires on the sub­strate in 2D ICs. It is the use of sil­i­con that makes them worthwhile.

The fab­ri­ca­tion tech­niques used for sil­i­con allow elec­tri­cal con­nec­tions much fin­er than fea­si­ble on com­mon sub­strates. More­over, we are not con­strained to con­nec­tions hor­i­zon­tal­ly but can also make them ver­ti­cal­ly. Thus, we can cre­ate many inter­con­nec­tions with­out a larg­er foot­print or adding much height. In turn, this means short­er sig­nal paths that enable high­er trans­mis­sion rates and reduce pow­er losses.

In addi­tion, sil­i­con expands much less when heat­ed than com­mon sub­strates. More impor­tant­ly, it expands like the dies mount­ed on top, whose microbumps must align per­fect­ly with the pads they con­nect to.


The most com­plex SiP uses dies on top of each oth­er. This is called 3D IC (three-dimen­sion­al inte­grat­ed circuit).

In its sim­plest form, one die is mount­ed on the top of anoth­er die, with the low­er die employ­ing through-sil­i­con vias (TSVs) to allow the upper die to con­nect to the low­er die and to the substrate.

In the gen­er­al case, a 3D IC con­sists of mul­ti­ple dies stacked on top of each oth­er using TSVs, and mul­ti­ple stacks of dies inter­con­nect­ed through a sil­i­con inter­pos­er. In jets, this is some­times called 5.5D IC since it com­bines the tech­niques of 2.5D and the sim­plest ver­sion of 3D.

Benefits of SiP

A sys­tem-in-pack­age (SiP) is the result of het­ero­ge­neous inte­gra­tion. Sim­ple dies are put togeth­er like Lego pieces to form com­plex sys­tems. As we have already not­ed, SiP pro­vides less foot­print, increased yield, increased trans­mis­sion speed, and less pow­er loss. Tak­en togeth­er, this opens the door to con­tin­ued rapid growth in per­for­mance per unit area despite the lit­er­al mean­ing of Moore’s law ceas­ing to apply.

How­ev­er, it is not enough to open the door; we must also get through it.

What’s next?

Sev­er­al things need to be addressed to main­tain con­tin­ued rapid growth in per­for­mance per unit area. In particular,

  • more con­nec­tors are need­ed for each die to han­dle more data,
  • heat must be dis­si­pat­ed from each die to avoid mal­func­tion, and
  • decou­pling capac­i­tors must be placed as close to each die as pos­si­ble to avoid interference.

These are chal­lenges that put bound­aries for what is pos­si­ble with het­ero­ge­neous inte­gra­tion. And we have accept­ed the challenge.

Pushes the boundaries of heterogeneous integration

Smoltek devel­ops tech­nolo­gies to fab­ri­cate nanos­truc­tures. In par­tic­u­lar, we are focus­ing on car­bon nanofibers (CNFs), which have many valu­able prop­er­ties. They are very stiff and strong. They are good con­duc­tors of heat and elec­tric­i­ty. And the con­tact sur­face where they stand increas­es a thousandfold.

A sig­nif­i­cant part of Smoltek’s research and devel­op­ment has been com­mit­ted to over­com­ing the chal­lenges of het­ero­ge­neous inte­gra­tion. We have also com­mit­ted our­selves to devel­op a fab­ri­ca­tion tech­nol­o­gy that is process com­pat­i­ble with CMOS. The latter’s chal­lenge is the rel­a­tive­ly low tem­per­a­tures used in CMOS fab­ri­ca­tion. We are pleased to say that we have deliv­ered on our commitments.

Smoltek’s achievements

We have developed

  • microbumps with ultra-fine pitch (< 5 µm),
  • ultra thin ther­mal film for heat dissipation,
  • an inter­pos­er with built-in DC stor­age smooth­ing out vari­a­tions in pow­er supply,
  • a capac­i­tor direct on die or embed­ded in interposers

These achieve­ments form the cor­ner­stones on which we have built Smoltek Tiger—an assem­bly plat­form con­cept for het­ero­ge­neous inte­gra­tion and advanced pack­ag­ings such as 2.5D and 3D SiP.

Of these achieve­ments, we are most excit­ed about our capac­i­tor, which has the world’s small­est foot­print (650 nF/​mm2) and low­est build height (0.5–10 µm). Its inter­nal resis­tance (ESR) is less than forty mil­liohms (40 mΩ), and its inter­nal induc­tance (ESL) is below fif­teen pico­hen­ry (15 pH). So, of course, we also want to make this tech­nol­o­gy avail­able as a reg­u­lar dis­crete component.

Ultra-miniaturized discrete capacitors

Capac­i­tors are essen­tial in all elec­tron­ics. They store ener­gy, atten­u­ate tran­sients, dis­si­pate inter­fer­ence, and more. They are indis­pens­able. Not least inside and out­side inte­grat­ed circuits.

We have there­fore focused in par­tic­u­lar on devel­op­ing our ultra-minia­tur­ized capac­i­tor and mak­ing it avail­able as a dis­crete com­po­nent that can be

  • mount­ed on chip die,
  • embed­ded in chip interposer,
  • mount­ed on chip interposer,
  • embed­ded in print­ed cir­cuit board (PCB), and
  • mount­ed on PCB.

The total height, includ­ing cap­sule, is only 30 µm—which is less than half what is pos­si­ble with oth­er technologies.

The most amaz­ing thing about this micro­scop­ic capac­i­tor is its per­for­mance. One square mil­lime­ter has a capac­i­tance of a whop­ping 650 nF/​mm2. Its inter­nal resis­tance (ESR) is less than 40 mΩ, and its inter­nal induc­tance (ESL) is below 15 pH.

We describe our capac­i­tor as a CNF-MIM capac­i­tor since it is a met­al-insu­la­tor-met­al (MIM) capac­i­tor where car­bon nanofibers (CNF) are used to cre­ate a much larg­er sur­face area hence high­er capac­i­tance than the form fac­tor suggest.

Read the ded­i­cat­ed page about Smoltek’s CNF-MIM capac­i­tor for more information.

Close-up of a wafer with Smoltek’s car­bon nanofiber met­al-insu­la­tor-met­al (CNF-MIM) capacitor—the world’s thinnest capacitor.

Interested in our technology?

Smoltek’s busi­ness mod­el is not to man­u­fac­ture semi­con­duc­tors nor capac­i­tors but to license our fab­ri­ca­tion tech­nol­o­gy to lead­ing sup­pli­ers of such products.

We offer a long-term tech­ni­cal part­ner­ship, where we con­tribute our tech­nol­o­gy which we have invest­ed mon­ey and time in devel­op­ing at our per­il, for the ben­e­fit of our part­ner, thus short­en­ing the devel­op­ment time and min­i­miz­ing the risks. We also offer know-how, tai­lor-made solu­tions, pro­duc­tion of test series, and advice and assis­tance in imple­ment­ing the man­u­fac­tur­ing process.

Are you inter­est­ed in part­ner­ing with us? Con­tact us today, and let’s arrange a meet­ing to dis­cuss it further.

Related insights from Smoltek

Hand held circular disc with Smoltek logo

Smoltek—from carbon nanofibers to mind-controlled robotic prostheses

Smoltek holds unique world patents for technologies that make material engineering on an atomic level possible. Smoltek has solutions that allow continued miniaturization and increased performance of semiconductors, contribute to carbon-free steel production and renewable energy storage, and enable mind control of robotic prostheses. This is a story of how Smoltek came to be.
Ola Tiverman, President Smoltek Semi

Operational update on the activities in Smoltek Semi

A main goal for Smoltek Semi is to develop an industrial process for mass production of discrete CNF-MIM capacitors at contract manufacturers (foundry), including a specially designed machine for large-scale production of carbon nanofibers.

Breaking barriers: The future

This is the third and last article in a series of three in which Smoltek founder and strategic advisor Shafiq Kabir share his personal thoughts on nanotechnology opportunities. In the previous two articles, he has addressed both the hype and the reality of carbon nanotechnology. In this last article, he looks into the future. He discusses how carbon nanotechnology will unleash the power of the internet of everything.

Breaking barriers: The hype

This is the first article in a series of three in which Smoltek founder and strategic advisor Shafiq Kabir share his personal thoughts on nanotechnology opportunities. This introductory article addresses the hype surrounding nanotechnology in general and carbon nanotechnology in particular.