Carbon nanofibers in the semiconductor industry

What are semiconductors?

A mater­i­al is an elec­tric­al con­duct­or if an elec­tric field can move an elec­tron from one atom to the next. Only the elec­tron in the out­er­most shell around an atom­ic nuc­le­us can do that, and only if there is an even fur­ther out shell that it can jump to with energy from the elec­tric field.

If the dis­tance between the out­er­most shell of elec­trons and the next shell is too great for elec­trons to jump out there, the sub­stance is an elec­tric­al insu­lat­or.

For some mater­i­als, such as sil­ic­on, the gap is so small that some elec­trons can jump across the gap. When the elec­tron crosses the gap, it leaves behind a hole. Under the influ­ence of an elec­tric­al field, both the elec­tron and the hole can move across the mater­i­al. It con­ducts elec­tri­city, but poorly. That’s why such a sub­stance is called semi­con­duct­or.

The con­duct­iv­ity can be dra­mat­ic­ally improved by adding impur­it­ies in the form of oth­er sub­stances that add extra elec­trons or holes. This is called n‑doping and p‑doping, respect­ively.

The magic at the p‑n-junction

A p‑n-junc­tion is where p‑doped semi­con­duct­or meets n‑doped semi­con­duct­or. At p‑n-junc­tions, the magic hap­pens that makes mod­ern elec­tron­ics possible.

Because there is an excess of elec­trons in the n‑doped semi­con­duct­or and a defi­cit of elec­trons (holes) in the p‑doped semi­con­duct­or, elec­trons dif­fuse from the n‑doped to the p‑doped semi­con­duct­or to reach equi­lib­ri­um. This cre­ates a region that is depleted of elec­trons and holes that can carry cur­rent. Con­sequently, the region is said to be a deple­tion region.

By apply­ing a voltage across the p‑n junc­tion one can cause the deple­tion region to increase (which blocks cur­rent from passing) or decrease (which allows cur­rent to pass). This is what is exploited in transistors.

How transistors work

A tran­sist­or acts like an elec­tric­ally con­trolled tap. By gently turn­ing the tap, more or less flow can be cre­ated. This fea­ture is used in ana­log elec­tron­ics to amp­li­fy sig­nals. By quickly turn­ing the tap on or off, “ones and zer­os” are cre­ated in terms of cur­rent passing or not. This is the found­a­tion of all digit­al elec­tron­ics, not least computers.

The first tran­sist­or was cre­ated in Decem­ber 1947 at the Bell Tele­phone Labor­at­or­ies. A couple of years later, what we today think of as a tran­sist­or was inven­ted. It con­sists of n‑doped or p‑doped semi­con­duct­ors through which cur­rent is passed. The middle part of the semi­con­duct­or is replaced by a piece of semi­con­duct­or of the oppos­ite type. It cre­ates two p‑n junc­tions. By sup­ply­ing cur­rent through the middle sec­tion, the width of the two deple­tion regions can be changed. Thus, a cur­rent through the middle sec­tion con­trols how much of the cur­rent through the tran­sist­or is allowed to pass. Since both neg­at­ive and pos­it­ive charges are mov­ing (elec­trons and elec­tron holes, respect­ively), it is called bipolar junc­tion tran­sist­or (BJT).

MOSFET

A tran­sist­or con­trolled by an elec­tric field instead of cur­rent is called a field-effect tran­sist­or (FET). While the BJT always con­sumes power, the FET con­sumes no power when its tap is unchanged (e.g., on or off). That’s per­fect for cre­at­ing energy-effi­cient digit­al electronics.

The first field-effect tran­sist­or was developed in 1953. But it had prob­lems with leak­aging cur­rent where p–n junc­tions inter­cept the surface.

In the late 1950s, Mohamed M. Atalla of Bell Tele­phone Labor­at­or­ies dis­covered that a thin lay­er of insu­lat­ing sil­ic­on diox­ide on top of a semi­con­duct­or pre­vents leak­age cur­rent. But how to make elec­tric con­tact with a FET if an insu­lat­ing lay­er cov­ers its surface?

Mohamed M. Atalla and his col­league Dawon Kahng eleg­antly solved this. They added met­al gates on top of the oxide lay­er where they wanted the con­nec­tion. The stack of met­al, oxide, and semi­con­duct­or form a par­al­lel-plate capa­cit­or. The met­al gate is one elec­trode, the semi­con­duct­or under­neath is the oth­er elec­trode, and the thin sil­ic­on diox­ide lay­er acts as the dielec­tric. The much improved FET was named met­al-oxide-semi­con­duct­or field-effect tran­sist­or, or MOSFET for short.

One of the MOS­FETs’ many bene­fits is that com­pared to BJTs they are rel­at­ively easy to pro­duce. There­fore, it is bet­ter to use MOS­FETs in integ­rated cir­cuits. Dawon Kahng poin­ted this out in 1961.

Integrated circuit (IC)—chip

An integ­rated cir­cuit (IC) is a set of elec­tron­ic cir­cuits on one small flat piece of semi­con­duct­or called chip. The idea of com­bin­ing sev­er­al com­pon­ents in one device goes back to 1949. But it wasn’t until a dec­ade later that the first IC in a mod­ern sense was fab­ric­ated. It used bipolar junc­tion tran­sist­ors (BJT). The first chip with MOSFET was fab­ric­ated in 1961.

MOS­FETs are super­i­or to BJTs in integ­rated cir­cuits because they are easi­er to pro­duce and can be made much smal­ler. It took only two years after the first MOSFET chip was pro­duced before chips with MOSFET reached high­er tran­sist­or dens­ity and lower man­u­fac­tur­ing costs than those with BJTs.

CMOS

In the late 1960s, the com­ple­ment­ary met­al-oxide-semi­con­duct­or (CMOS) was developed. The name refers to both a par­tic­u­lar style of digit­al cir­cuitry design, cre­at­ing digit­al gates by com­bin­ing two MOS­FETs of oppos­ite dop­ing, and a pro­cess used to imple­ment that cir­cuitry on integ­rated cir­cuits (chips). Two import­ant char­ac­ter­ist­ics of CMOS devices are high noise immunity and low stat­ic power consumption.

Chip manufacturing process

The pro­duc­tion of chips is a com­plex pro­cess that can take up to three months. Today, they are usu­ally man­u­fac­tured accord­ing to the fol­low­ing steps:

1. Extremely pure sil­ic­one is pro­duced from quartzite or sand. The sil­ic­one is shaped into a cyl­indric­al ingot with a dia­met­er of up to 300 mil­li­meters. The sil­ic­on ingot is then sliced into discs; each disc is 0.75 mil­li­meters thick and is called a wafer.
2. Sev­er­al thin lay­ers of insu­lat­ing, semi­con­duct­ing, and con­duct­ing mater­i­als are placed on a wafer. Which mater­i­als and in what order depends on what is to be pro­duced. This is called depos­ition.
3. The last lay­er applied is a photores­ist—a sub­stance res­ist­ant to cor­ros­ive sub­stances except where it has been exposed to ultra­vi­olet light.
4. The next step is litho­graphy. Deep ultra­vi­olet (DUV) or extreme ultra­vi­olet (EUV) light is sent through a ret­icle with the draw­ing of the pat­tern to be cre­ated. Lenses or mir­rors are used to shrink and focus the pat­tern pro­jec­ted onto the photores­ist. Where the light hits the photores­ist, it loses its res­ist­ance to cor­ros­ive sub­stances, while the res­ist­ance remains where the light has not hit.
5. Wafers are now placed in a chem­ic­al bath that erodes exposed photores­ist while leav­ing the unex­posed photores­ist unaf­fected. This is called wet etch­ing. Instead of a bath, gas can also be used. This is called dry etch­ing. The res­ult is that under­ly­ing lay­ers are uncovered where the light has hit while the rest is still shielded.
6. Once pat­terns are etched in the wafer, the wafer may be bom­barded with pos­it­ive or neg­at­ive ions to dope uncovered semi­con­duct­ors. This is called ion implant­a­tion.
7. Now, the remain­ing sec­tions of res­ist that were pro­tect­ing areas that should not be etched or ion­ized are removed.
8. Steps 2–7 are repeated repeatedly until the desired func­tion­al­ity is achieved. Mod­ern chips can have up to two hun­dred lay­ers, which all need to align on top of each oth­er with extreme precision.
9. A wafer holds cir­cuits for many chips. How many cir­cuits depends on how large they are. Some wafers may con­tain thou­sands of cir­cuits, while oth­ers con­tain only a few dozen. The cir­cuits are cut out with a dia­mond saw. The cut-out pieces of the wafer are called dies.
10. The chip is now cre­ated by mount­ing the die on a sub­strate that acts as a back­plane with con­nect­ing wires.
11. Finally, the chip is put into a plastic pack­age with con­nect­ing pins.

Minimum costs per transistor

Although chip man­u­fac­tur­ing has been refined since the first MOSFET chips were pro­duced, not all dies will work. There­fore, each die must be tested (which is typ­ic­ally done before the wafer is diced). The per­cent­age that passes is called the die yield.

The cost per tran­sist­or decreases with the num­ber of tran­sist­ors that fit on a chip to a point where the cost increases again due to decreas­ing yield. Thus there is an inflec­tion point where the cost per tran­sist­or is the low­est possible.

In an art­icle pub­lished in 1965 in Elec­tron­ics (Volume 38, Num­ber 8), Gor­don E. Moore—co-founder of Fairchild Semi­con­duct­or and later Intel—referred to this optim­al point as “min­im­um com­pon­ent costs.” Moreover, he noted that in those few years that chips had been pro­duced, the num­ber of tran­sist­ors giv­ing min­im­um com­pon­ent costs had doubled each year. He pre­dicted that this growth rate would con­tin­ue for anoth­er ten years.

Moore’s law

When he looked back at his pre­dic­tion in 1975, Moore, who now was CEO of Intel, found it was almost spot on. Instead of an expec­ted increase of 2¹⁰, the increase was 2⁹. In oth­er words, the num­ber of tran­sist­ors at the low­est price point doubled every 13 months.

At the 1975 IEEE Inter­na­tion­al Elec­tron Devices Meet­ing, Moore revised his fore­cast rate, pre­dict­ing that semi­con­duct­or com­plex­ity would con­tin­ue to double annu­ally until about 1980, after which it would decrease to a rate of doub­ling approx­im­ately every two years.

One of Moore’s friends, Dr. Carv­er Mead, a pro­fess­or at Cal­tech, dubbed this revised pre­dic­tion as Moore’s Law.

House’s postulate

In a sci­entif­ic paper pub­lished in 1974, the power con­sump­tion of MOS­FETs was shown to decrease lin­early with the area they occupy. This rela­tion­ship is called Dennard scal­ing.

Dennard’s scal­ing makes it pos­sible to double the num­ber of tran­sist­ors without using more power. And if no more power is sup­plied, no more heat needs to be dis­sip­ated. Thus it is pos­sible to double the com­pu­ta­tion­al capa­city by doub­ling the num­ber of tran­sist­ors without heat dis­sip­a­tion becom­ing a grow­ing prob­lem. This leaves room to increase the clock fre­quency that sets the rate at which ones and zer­os are turned off and on.

Dav­id House, an Intel exec­ut­ive, real­ized that this and oth­er improve­ments make it pos­sible to increase com­put­ing capa­city faster than the num­ber of tran­sist­ors. He, there­fore, pos­tu­lated that the per­form­ance of a com­puter chip doubles every eight­een months.

House’s pos­tu­lates are often mis­taken as Moore’s Law. But these are two sep­ar­ate pre­dic­tions, albeit closely related.

Is Moore’s law still applicable?

Does Moore’s law still apply? No, not as ori­gin­ally for­mu­lated. Dens­ity at min­im­um cost per tran­sist­or has long ceased to double every two years. How­ever, dens­ity at any cost per tran­sist­or still doubles every two years.

But even this more gen­er­ous inter­pret­a­tion of Moore’s law will not last forever. Many industry experts believe that Moore’s law will cease to apply alto­geth­er as early as 2025.

Reas­ons for Moore’s law to cease are many. Obvi­ously, tran­sist­ors can­not become smal­ler than the atoms that make them up. But even before that, prob­lems arise with quantum tun­nel­ing, where elec­trons jump through bar­ri­ers and cause cur­rent leak­age. Anoth­er prob­lem, which is already real, is para­sit­ic tran­sist­ors that cre­ate cir­cuits that shouldn’t be there.

Does it matter?

Does it mat­ter that Moore’s law is com­ing to an end? Not per se, but its implic­a­tions are profound.

The devel­op­ment of the Inter­net of Things (IoT), self-driv­ing cars, con­nec­ted homes, Vir­tu­al Real­ity (VR), and Arti­fi­cial Intel­li­gence (AI) increas­ingly demands high com­put­ing capa­city in a small foot­print and at low power con­sump­tion. For this devel­op­ment not to come to a halt with Moore’s law, oth­er solu­tions are needed than cram­ming more and more tran­sist­ors onto the same surface.

A fore­cast of what will hap­pen when Moore’s Law ceases to apply was giv­en to the semi­con­duct­or industry around 2006 when Dennard scal­ing broke down.

Breakdown of Dennard scaling

The power con­sump­tion of CMOS cir­cuits is pro­por­tion­al to the clock fre­quency. His­tor­ic­ally, the tran­sist­or power reduc­tion afforded by Dennard scal­ing allowed man­u­fac­tur­ers to raise clock fre­quen­cies from one gen­er­a­tion to the next without sig­ni­fic­antly increas­ing over­all cir­cuit power consumption.

But around 2006, tran­sist­ors had shrunken so much the power required to run them increased due to cur­rent leak­age. Increased power con­sump­tion leads to increased heat gen­er­a­tion. And increased heat causes elec­trons to become more mobile, which can cause tran­sist­ors to turn on or off spon­tan­eously, lead­ing to fatal fail­ures. Increased heat also increases leak­age cur­rent, which fur­ther increases power con­sump­tion and the prob­lems that fol­low. In the worst case, this self-amp­li­fic­a­tion can lead to thermal runaway.

Overcoming the Dennard scaling breakdown

The break­down of Dennard scal­ing promp­ted a prob­lem that could only be par­tially over­come with improved cool­ing. In the end, it was not reas­on­able to con­tin­ue increas­ing the clock speed. That’s why the clock fre­quency of today’s micro­pro­cessors is the same as fif­teen years ago. But the per­form­ance has increased any­way. How?

The solu­tion to over­come the break­down of Dennard scal­ing was multi-core pro­cessors. Instead of increas­ing the speed at which a single pro­cessing unit executed instruc­tions, more units were added. These units, called cores, can work inde­pend­ently with par­al­lel tasks. This increases the over­all per­form­ance of the processor.

The solu­tion when Moore’s law breaks down is kind of similar.

System-in-Package (SiP)

The final step in fab­ric­at­ing integ­rated cir­cuits is to place the chip into a plastic pack­age with con­nect­ing pins. In the begin­ning, each such pack­age con­tained only one chip. Even­tu­ally, two or more chips began to be placed in the same pack­age to cope with

• reduced sur­face area due to more and more to be packed into less and less space,
• reduced yield due to lar­ger dies,
• lim­ited trans­mis­sion speed due to capa­cit­ance in long wires, and
• power losses due to para­sit­ic capa­cit­ance in long wires.

It also allows the assembly of sim­pler chips into more com­plex solutions—like Lego. Lastly, it enables a mix of chips with incom­pat­ible man­u­fac­tur­ing and pass­ive com­pon­ents (e.g. condensers).

This approach is called het­ero­gen­eous integ­ra­tion, and the res­ult is called a Sys­tem-in-Pack­age or SiP for short.

2D IC

The easi­est way is to assemble a SiP is to place two or more dies next to each oth­er on the same sub­strate. The dies are inter­con­nec­ted with each oth­er through wires in the sub­strate. The sub­strate also provides an extern­al con­nec­tion through tiny globes of solder—called solder bumps.

A die can be moun­ted face up. Then the die is con­nec­ted to the inter­con­nec­tions and the solder bumps with wires.

More com­mon is to mount a die face down. In this case, the die itself has micro­scop­ic solder globes—called microbumps—that come into con­tact with pads on the top of the sub­strate. These pads are, in turn, con­nec­ted to the substrate’s inter­con­nec­tions and solder bumps.

This form of SiP is called 2D IC (two-dimen­sion­al integ­rated cir­cuit) because the dies are moun­ted in a single plane. It is also known as multi-chip mod­ule (MCM).

2.5D IC

The next step up in SiP-com­plex­ity is called 2.5D IC (two and a half-dimen­sion­al integ­rated cir­cuit). The name comes from the fact that dies are still side by side, but now face down on an inter­me­di­ate lay­er of silicon—called inter­poser. An inter­poser has pads on its top and microbumps on its bot­tom. Hori­zont­al elec­tric­al con­nec­tions inside the sil­ic­on inter­con­nect some pads. Some are con­nec­ted to microbumps by a ver­tic­al elec­tric­al con­nec­tion run­ning through the silicon—called through sil­ic­on via or TSV for short.

So what’s the point of adding an inter­poser? An inter­poser gen­er­ally reroutes con­nec­tions from one con­fig­ur­a­tion and pitch to anoth­er con­fig­ur­a­tion and pitch. But this is not the primary reas­on for their use in 2.5D ICs; the same goal can be achieved with wires on the sub­strate in 2D ICs. It is the use of sil­ic­on that makes them worthwhile.

The fab­ric­a­tion tech­niques used for sil­ic­on allow elec­tric­al con­nec­tions much finer than feas­ible on com­mon sub­strates. Moreover, we are not con­strained to con­nec­tions hori­zont­ally but can also make them ver­tic­ally. Thus, we can cre­ate many inter­con­nec­tions without a lar­ger foot­print or adding much height. In turn, this means short­er sig­nal paths that enable high­er trans­mis­sion rates and reduce power losses.

In addi­tion, sil­ic­on expands much less when heated than com­mon sub­strates. More import­antly, it expands like the dies moun­ted on top, whose microbumps must align per­fectly with the pads they con­nect to.

3D IC

The most com­plex SiP uses dies on top of each oth­er. This is called 3D IC (three-dimen­sion­al integ­rated circuit).

In its simplest form, one die is moun­ted on the top of anoth­er die, with the lower die employ­ing through-sil­ic­on vias (TSVs) to allow the upper die to con­nect to the lower die and to the substrate.

In the gen­er­al case, a 3D IC con­sists of mul­tiple dies stacked on top of each oth­er using TSVs, and mul­tiple stacks of dies inter­con­nec­ted through a sil­ic­on inter­poser. In jets, this is some­times called 5.5D IC since it com­bines the tech­niques of 2.5D and the simplest ver­sion of 3D.

Benefits of SiP

A sys­tem-in-pack­age (SiP) is the res­ult of het­ero­gen­eous integ­ra­tion. Simple dies are put togeth­er like Lego pieces to form com­plex sys­tems. As we have already noted, SiP provides less foot­print, increased yield, increased trans­mis­sion speed, and less power loss. Taken togeth­er, this opens the door to con­tin­ued rap­id growth in per­form­ance per unit area des­pite the lit­er­al mean­ing of Moore’s law ceas­ing to apply.

How­ever, it is not enough to open the door; we must also get through it.

What’s next?

Sev­er­al things need to be addressed to main­tain con­tin­ued rap­id growth in per­form­ance per unit area. In particular,

• more con­nect­ors are needed for each die to handle more data,
• heat must be dis­sip­ated from each die to avoid mal­func­tion, and
• decoup­ling capa­cit­ors must be placed as close to each die as pos­sible to avoid interference.

These are chal­lenges that put bound­ar­ies for what is pos­sible with het­ero­gen­eous integ­ra­tion. And we have accep­ted the challenge.

Pushes the boundaries of heterogeneous integration

Smol­tek devel­ops tech­no­lo­gies to fab­ric­ate nano­struc­tures. In par­tic­u­lar, we are focus­ing on car­bon nan­ofibers (CNFs), which have many valu­able prop­er­ties. They are very stiff and strong. They are good con­duct­ors of heat and elec­tri­city. And the con­tact sur­face where they stand increases a thousandfold.

A sig­ni­fic­ant part of Smoltek’s research and devel­op­ment has been com­mit­ted to over­com­ing the chal­lenges of het­ero­gen­eous integ­ra­tion. We have also com­mit­ted ourselves to devel­op a fab­ric­a­tion tech­no­logy that is pro­cess com­pat­ible with CMOS. The latter’s chal­lenge is the rel­at­ively low tem­per­at­ures used in CMOS fab­ric­a­tion. We are pleased to say that we have delivered on our commitments.

Smoltek’s achievements

We have developed

• microbumps with ultra-fine pitch (< 5 µm),
• ultra thin thermal film for heat dissipation,
• an inter­poser with built-in DC stor­age smooth­ing out vari­ations in power supply,
• a capa­cit­or dir­ect on die or embed­ded in interposers

These achieve­ments form the corner­stones on which we have built Smol­tek Tiger—an assembly plat­form concept for het­ero­gen­eous integ­ra­tion and advanced pack­agings such as 2.5D and 3D SiP.

Of these achieve­ments, we are most excited about our capa­cit­or, which has the world’s smal­lest foot­print (650 nF/​mm²) and low­est build height (0.5–10 µm). Its intern­al res­ist­ance (ESR) is less than forty mil­liohms (40 mΩ), and its intern­al induct­ance (ESL) is below fif­teen pico­henry (15 pH). So, of course, we also want to make this tech­no­logy avail­able as a reg­u­lar dis­crete component.

Ultra-miniaturized discrete capacitors

Capa­cit­ors are essen­tial in all elec­tron­ics. They store energy, atten­u­ate tran­si­ents, dis­sip­ate inter­fer­ence, and more. They are indis­pens­able. Not least inside and out­side integ­rated circuits.

We have there­fore focused in par­tic­u­lar on devel­op­ing our ultra-mini­atur­ized capa­cit­or and mak­ing it avail­able as a dis­crete com­pon­ent that can be

• moun­ted on chip die,
• embed­ded in chip interposer,
• moun­ted on chip interposer,
• embed­ded in prin­ted cir­cuit board (PCB), and
• moun­ted on PCB.

The total height, includ­ing cap­sule, is only 30 µm—which is less than half what is pos­sible with oth­er technologies.

The most amaz­ing thing about this micro­scop­ic capa­cit­or is its per­form­ance. One square mil­li­meter has a capa­cit­ance of a whop­ping 650 nF/​mm². Its intern­al res­ist­ance (ESR) is less than 40 mΩ, and its intern­al induct­ance (ESL) is below 15 pH.

We describe our capa­cit­or as a CNF-MIM capa­cit­or since it is a met­al-insu­lat­or-met­al (MIM) capa­cit­or where car­bon nan­ofibers (CNF) are used to cre­ate a much lar­ger sur­face area hence high­er capa­cit­ance than the form factor suggest.

Read the ded­ic­ated page about Smoltek’s CNF-MIM capa­cit­or for more information.

Interested in our technology?

Smoltek’s busi­ness mod­el is not to man­u­fac­ture semi­con­duct­ors nor capa­cit­ors but to license our fab­ric­a­tion tech­no­logy to lead­ing sup­pli­ers of such products.

We offer a long-term tech­nic­al part­ner­ship, where we con­trib­ute our tech­no­logy which we have inves­ted money and time in devel­op­ing at our per­il, for the bene­fit of our part­ner, thus short­en­ing the devel­op­ment time and min­im­iz­ing the risks. We also offer know-how, tail­or-made solu­tions, pro­duc­tion of test series, and advice and assist­ance in imple­ment­ing the man­u­fac­tur­ing process.

Are you inter­ested in part­ner­ing with us? Con­tact us today, and let’s arrange a meet­ing to dis­cuss it further.