Author: S Kabir

Interposer

Interposer

The inven­tion: An inter­pos­er device com­pris­ing an inter­pos­er sub­strate; a plu­ral­i­ty of con­duct­ing vias extend­ing through the inter­pos­er sub­strate; a con­duc­tor pat­tern on the inter­pos­er sub­strate, and a nanos­truc­ture ener­gy stor­age device. The nanos­truc­ture ener­gy stor­age device com­pris­es at least a first plu­ral­i­ty of con­duc­tive nanos­truc­tures formed on the inter­pos­er sub­strate; a con­duc­tion con­trol­ling mate­r­i­al embed­ding each nanos­truc­ture in the first plu­ral­i­ty of con­duc­tive nanos­truc­tures; a first elec­trode con­nect­ed to each nanos­truc­ture in the first plu­ral­i­ty of nanos­truc­tures; and a sec­ond elec­trode sep­a­rat­ed from each nanos­truc­ture in the first plu­ral­i­ty of nanos­truc­tures by the con­duc­tion con­trol­ling mate­r­i­al, where­in the first elec­trode and the sec­ond elec­trode are con­fig­ured to allow elec­tri­cal con­nec­tion of the nanos­truc­ture ener­gy stor­age device to the inte­grat­ed circuit.

Nanostructure device and method for manufacturing nanostructures

Nanostructure device and method for manufacturing nanostructures

A method for man­u­fac­tur­ing a plu­ral­i­ty of nanos­truc­tures on a sub­strate. The method com­pris­es the steps of: deposit­ing a bot­tom lay­er on an upper sur­face of the sub­strate, the bot­tom lay­er com­pris­ing grains hav­ing a first aver­age grain size; deposit­ing a cat­a­lyst lay­er on an upper sur­face of the bot­tom lay­er, the cat­a­lyst lay­er com­pris­ing grains hav­ing a sec­ond aver­age grain size dif­fer­ent from the first aver­age grain size, there­by form­ing a stack of lay­ers com­pris­ing the bot­tom lay­er and the cat­a­lyst lay­er; heat­ing the stack of lay­ers to a tem­per­a­ture where nanos­truc­tures can form; and pro­vid­ing a gas com­pris­ing a reac­tant such that the reac­tant comes into con­tact with the cat­a­lyst layer.

Template and method of making high aspect ratio template for lithography and use of the template for perforating a substrate at nanoscale

Template and method of making high aspect ratio template for lithography and use of the template for perforating a substrate at nanoscale

Tem­plate and method of mak­ing high aspect ratio tem­plate, stamp, and imprint­ing at nanoscale using nanos­truc­tures for the pur­pose of lith­o­g­ra­phy, and to the use of the tem­plate to cre­ate per­fo­ra­tions on mate­ri­als and products.

Deposition and selective removal of conducting helplayer for nanostructure processing

Deposition and selective removal of conducting helplayer for nanostructure processing

A method for mak­ing one or more nanos­truc­tures is dis­closed, the method com­pris­ing: deposit­ing a con­duct­ing lay­er on an upper sur­face of a sub­strate; deposit­ing a pat­terned lay­er of cat­a­lyst on the con­duct­ing lay­er; grow­ing the one or more nanos­truc­tures on the lay­er of cat­a­lyst; and selec­tive­ly remov­ing the con­duct­ing lay­er between and around the one or more nanos­truc­tures. A device is also dis­closed, com­pris­ing a sub­strate, where­in the sub­strate com­pris­es one or more exposed met­al islands sep­a­rat­ed by one or more insu­lat­ing areas; a con­duct­ing helplay­er dis­posed on the sub­strate cov­er­ing at least some of the one or more exposed met­al islands or insu­lat­ing areas; a cat­a­lyst lay­er dis­posed on the con­duct­ing helplay­er; and one or more nanos­truc­tures dis­posed on the cat­a­lyst layer.