Patents

Smoltek uses a glob­al patent strat­e­gy to pro­tect our tech­nol­o­gy plat­form in all impor­tant mar­kets. This includes core patents as well as patent pro­tec­tion at appli­ca­tion lev­el. At present, we have a patent port­fo­lio that com­pris­es about 110 applied and pend­ing patents, dis­trib­uted among 20 patent fam­i­lies, of which 76 are granted. 

The strate­gic and con­tin­u­ous devel­op­ment of our patent port­fo­lio is dri­ven by the need for dis­rup­tive mate­ri­als and tech­ni­cal solu­tions that enables indus­tri­al­ly com­pat­i­ble fab­ri­ca­tion of nanos­truc­tures for var­i­ous appli­ca­tions, like ultra-thin capac­i­tors and new high-per­for­mance cell mate­r­i­al for electrolyzers. 

Our inno­v­a­tive tech­nol­o­gy plat­form is pro­tect­ed with an IP-port­fo­lio of +110 patents grant­ed and pend­ing, as well as a sig­nif­i­cant body of know-how and trade secrets.

Compact Energy Storage Interposer

Compact Energy Storage Interposer

The inven­tion: An inter­pos­er device com­pris­ing a first con­duc­tor pat­tern on a first side defin­ing a por­tion of the inter­pos­er device to be cov­ered by a first elec­tri­cal cir­cuit ele­ment; and a sec­ond con­duc­tor pat­tern on a sec­ond side to be con­nect­ed to a sec­ond elec­tri­cal cir­cuit ele­ment. The sec­ond con­duc­tor pat­tern is elec­tri­cal­ly cou­pled to the first con­duc­tor pat­tern. The inter­pos­er device fur­ther com­pris­es a plu­ral­i­ty of nanos­truc­ture ener­gy stor­age devices arranged with­in the por­tion of the inter­pos­er device to be cov­ered by the first elec­tri­cal cir­cuit ele­ment. Each of the nanos­truc­ture ener­gy stor­age devices com­pris­es at least a first plu­ral­i­ty of con­duc­tive nanos­truc­tures; a con­duc­tion con­trol­ling mate­r­i­al embed­ding the nanos­truc­tures; a first elec­trode con­nect­ed to each nanos­truc­ture in the first plu­ral­i­ty of nanos­truc­tures; and a sec­ond elec­trode sep­a­rat­ed from each nanos­truc­ture in the first plu­ral­i­ty of nanos­truc­tures by the con­duc­tion con­trol­ling material.

Assembly platform

Assembly platform

The inven­tion: An assem­bly plat­form for arrange­ment as an inter­pos­er device between an inte­grat­ed cir­cuit and a sub­strate to inter­con­nect the inte­grat­ed cir­cuit and the sub­strate through the assem­bly plat­form, the assem­bly plat­form com­pris­ing: an assem­bly sub­strate; a plu­ral­i­ty of con­duct­ing vias extend­ing through the assem­bly sub­strate; at least one nanos­truc­ture con­nec­tion bump on a first side of the assem­bly sub­strate, the nanos­truc­ture con­nec­tion bump being con­duc­tive­ly con­nect­ed to the vias and defin­ing con­nec­tion loca­tions for con­nec­tion with at least one of the inte­grat­ed cir­cuit and the sub­strate, where­in each of the nanos­truc­ture con­nec­tion bumps com­pris­es: a plu­ral­i­ty of elon­gat­ed con­duc­tive nanos­truc­tures ver­ti­cal­ly grown on the first side of the assem­bly sub­strate, where­in the plu­ral­i­ty of elon­gat­ed nanos­truc­tures are embed­ded in a met­al for the con­nec­tion with at least one of the inte­grat­ed cir­cuit and the sub­strate, at least one con­nec­tion bump on a sec­ond side of the assem­bly sub­strate, the sec­ond side being oppo­site to the first side, the con­nec­tion bump being con­duc­tive­ly con­nect­ed to the vias and defin­ing con­nec­tion loca­tions for con­nec­tion with at least one of the inte­grat­ed cir­cuit and the substrate.

Interposer

Interposer

The inven­tion: An inter­pos­er device com­pris­ing an inter­pos­er sub­strate; a plu­ral­i­ty of con­duct­ing vias extend­ing through the inter­pos­er sub­strate; a con­duc­tor pat­tern on the inter­pos­er sub­strate, and a nanos­truc­ture ener­gy stor­age device. The nanos­truc­ture ener­gy stor­age device com­pris­es at least a first plu­ral­i­ty of con­duc­tive nanos­truc­tures formed on the inter­pos­er sub­strate; a con­duc­tion con­trol­ling mate­r­i­al embed­ding each nanos­truc­ture in the first plu­ral­i­ty of con­duc­tive nanos­truc­tures; a first elec­trode con­nect­ed to each nanos­truc­ture in the first plu­ral­i­ty of nanos­truc­tures; and a sec­ond elec­trode sep­a­rat­ed from each nanos­truc­ture in the first plu­ral­i­ty of nanos­truc­tures by the con­duc­tion con­trol­ling mate­r­i­al, where­in the first elec­trode and the sec­ond elec­trode are con­fig­ured to allow elec­tri­cal con­nec­tion of the nanos­truc­ture ener­gy stor­age device to the inte­grat­ed circuit.

Nanostructure device and method for manufacturing nanostructures

Nanostructure device and method for manufacturing nanostructures

A method for man­u­fac­tur­ing a plu­ral­i­ty of nanos­truc­tures on a sub­strate. The method com­pris­es the steps of: deposit­ing a bot­tom lay­er on an upper sur­face of the sub­strate, the bot­tom lay­er com­pris­ing grains hav­ing a first aver­age grain size; deposit­ing a cat­a­lyst lay­er on an upper sur­face of the bot­tom lay­er, the cat­a­lyst lay­er com­pris­ing grains hav­ing a sec­ond aver­age grain size dif­fer­ent from the first aver­age grain size, there­by form­ing a stack of lay­ers com­pris­ing the bot­tom lay­er and the cat­a­lyst lay­er; heat­ing the stack of lay­ers to a tem­per­a­ture where nanos­truc­tures can form; and pro­vid­ing a gas com­pris­ing a reac­tant such that the reac­tant comes into con­tact with the cat­a­lyst layer.

Template and method of making high aspect ratio template for lithography and use of the template for perforating a substrate at nanoscale

Template and method of making high aspect ratio template for lithography and use of the template for perforating a substrate at nanoscale

Tem­plate and method of mak­ing high aspect ratio tem­plate, stamp, and imprint­ing at nanoscale using nanos­truc­tures for the pur­pose of lith­o­g­ra­phy, and to the use of the tem­plate to cre­ate per­fo­ra­tions on mate­ri­als and products.

Deposition and selective removal of conducting helplayer for nanostructure processing

Deposition and selective removal of conducting helplayer for nanostructure processing

A method for mak­ing one or more nanos­truc­tures is dis­closed, the method com­pris­ing: deposit­ing a con­duct­ing lay­er on an upper sur­face of a sub­strate; deposit­ing a pat­terned lay­er of cat­a­lyst on the con­duct­ing lay­er; grow­ing the one or more nanos­truc­tures on the lay­er of cat­a­lyst; and selec­tive­ly remov­ing the con­duct­ing lay­er between and around the one or more nanos­truc­tures. A device is also dis­closed, com­pris­ing a sub­strate, where­in the sub­strate com­pris­es one or more exposed met­al islands sep­a­rat­ed by one or more insu­lat­ing areas; a con­duct­ing helplay­er dis­posed on the sub­strate cov­er­ing at least some of the one or more exposed met­al islands or insu­lat­ing areas; a cat­a­lyst lay­er dis­posed on the con­duct­ing helplay­er; and one or more nanos­truc­tures dis­posed on the cat­a­lyst layer.

Integrated circuits having interconnects and heat dissipators based on nanostructures

Integrated circuits having interconnects and heat dissipators based on nanostructures

The present inven­tion relates to a heat dis­si­pa­tor that includes a con­duc­tive sub­strate and a plu­ral­i­ty of nanos­truc­tures sup­port­ed by the con­duc­tive sub­strate. The nanos­truc­tures are at least part­ly embed­ded in an insu­la­tor. Each of the nanos­truc­tures includes a plu­ral­i­ty of inter­me­di­ate lay­ers on the con­duc­tive sub­strate. At least two of the plu­ral­i­ty of inter­me­di­ate lay­ers are inter­dif­fused, and mate­r­i­al of the at least two of the plu­ral­i­ty of inter­me­di­ate lay­ers that are inter­dif­fused is present in the nanostructure.

Controlled growth of a nanostructure on a substrate, and electron emission devices based on the same

Controlled growth of a nanostructure on a substrate, and electron emission devices based on the same

The present inven­tion pro­vides a method for nanos­truc­tures grown on a met­al under­lay­er, and a method of mak­ing the same. The grown nanos­truc­tures based on the claimed method are suit­able for man­u­fac­tur­ing elec­tron­ic devices such as an elec­tron beam writer, and a field emis­sion display.